VLSI Design Engineer

AdvanSoft

5 - 9 Years
100 Openings
15.0-40.0 Lac/Yr
Hyderabad
Face-to-Face interview

Key Skills

C Language VLSI-Very Large Scale Integration EDA System Verilog ASIC Verification RTL GLS UVM

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Job Description

Work Location: Bangalore / Hyderabad / Coimbatore.

EXP- 5+

Design Verification

- Strong UVM/SV

- IP and SOC DV

- AXI

- 5+ need to have strong protocol Exp such as DDR. PCIe, Ethernet

Design Verification - Gate Level Simulations (GLS)

- Gate Level Simulation (GLS) knowledge is must

- IP and SOC DV

- 5+ need to have strong GLS exp

RTL Design

- NO FPGA engineers. They shall have worked on ASIC flow

- Keywords - SPYGLASS, LEC, LINT, Synthesis,

Emulation

- UVM/SV

- Synopsys Zebu

- Transactor development OR running design with Firmware on Zebu

FORMAL - Design Verification

- Strong UVM/SV

- Experience on Cadence Jasper Gold or Incisive formal verifier (IFV)

- Connectivity Check, Register Validation etc.

- 7+ need to have some protocol