VLSI Design Engineer

AdvanSoft

Work Location: Bangalore / Hyderabad / Coimbatore.

EXP- 5+

Design Verification

- Strong UVM/SV

- IP and SOC DV

- AXI

- 5+ need to have strong protocol Exp such as DDR. PCIe, Ethernet

Design Verification - Gate Level Simulations (GLS)

- Gate Level Simulation (GLS) knowledge is must

- IP and SOC DV

- 5+ need to have strong GLS exp

RTL Design

- NO FPGA engineers. They shall have worked on ASIC flow

- Keywords - SPYGLASS, LEC, LINT, Synthesis,

Emulation

- UVM/SV

- Synopsys Zebu

- Transactor development OR running design with Firmware on Zebu

FORMAL - Design Verification

- Strong UVM/SV

- Experience on Cadence Jasper Gold or Incisive formal verifier (IFV)

- Connectivity Check, Register Validation etc.

- 7+ need to have some protocol

• Experience

  5 - 9 Years

• No. of Openings

  100

• Education

  B.A, Diploma, Any Bachelor Degree, Professional Degree

• Role

  VLSI Design Engineer

• Industry Type

  IT-Hardware & Networking / IT-Software / Software Services

• Gender

  [ Male / Female ]

• Job Country

  India

• Type of Job

  Full Time

• Work Location Type

  Work from Office