Role Purpose :
The incumbent will be involved in Synthesis and Timing closure of products related to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars from the stable of leading car manufacturers ( Eg-Daimler,-Benz, BMW, VOLVO).
Role Description:
• Participate on a project involved in the development of ASICs, with emphasis in Constraint development, Synthesis, Static Timing Analysis (STA), Power Estimation and driving clock tree synthesis.
• Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.
Responsibilities include but not limited to:
• Work closely with RTL design, DFT, Place and Route Implementation, low power and Power estimation teams to optimize Performance, Power and Area (PPA) for state of the art SOCs
• Proficient in constraint generation and validation
• Tabulate metrics results for analysis comparison
• Develop Rapid Timing Convergence Methodologies and Automation for optimal PPA
• Knowledge of Complete ASIC flow with low power, performance and area optimization techniques. Knowledge of full RTL to GDSII flow to take timing closure from RTL to signoff
• Strong problem solving and ASIC development/debugging skills
• High speed CPU implementation
• Clock Tree Implementation Techniques for High Speed Design Implementation are required
Technical background/Key Skills:
• experience with Synopsys/Cadence Synthesis and Timing SignOff tools are absolute must
• Formal verification experience (Formality/Conformal)
• Perl/Tcl, Python, C++ skills are needed
• Verilog coding experience
• Low power implementation techniques experience
4 - 10 Years
5 Openings
Not Disclosed
Bangalore 
Face-to-Face interview
Similar Jobs
Higher Boosting
Resume Highlighter
Verified Stamp
Resume Exposure
