This role is an exciting opportunity for a ASIC designer to contribute in a team of highly skilled design engineers within the SouthBridge IO (SBIO) team. Provide IP technical management and support for the end-to-end design development flow. This includes from architecture, microarchitecture, RTL design, design metrics (performance, power, area) analysis and design for verification strategy. Collaborate with design and verification teams to ensure a predictable IP development.
• Exhibits relentless commitment to help the team meet quality and development goals on schedule
• Drives to learn and perform at his or her highest potential in a technical capacity
• Thrives in both a team environment and in individual contribution
• Communicates openly and clearly in meetings, presentations, emails, and reports
• Able to learn independently and acquire new skills required for the job
• Creative and innovator and thinker who loves technical problems and detail-oriented tasks
KEY RESPONSIBLITIES:
• IP RTL design for USB IP used for all next generation server, clients, GPU and Semicustom products.
• Work closely with IP and system architects to micro-architect cutting edge features.
• Apply low power design techniques to existing logic and maintain overall system
performance.
• Focus on timing, LINT and CDC closure to ensure high quality RTL.
• Support verification and debug of the ASIC throughout various stages of the project.
• Jump into the lab and solve post silicon bring-up or customer issues.
• Analyze complex digital design problems and propose solutions.
• Develop Verilog RTL and Functional Behavioral Models.
• Drive/develop ASIC design flows and scripts.
• Create microarchitecture specifications.
• Work with Design Verification team to ensure functional correctness.
• Work with Physical Design team to ensure proper implementation of the design along with timing closure.
• Deliver improvements, optimization and power saving enhancements. At least 4 years’ experience