Requirements often include:
Strong proficiency in Verilog/VHDL or SystemVerilog.
Knowledge of digital design principles.
Understanding of ASIC design flows.
Experience with synthesis, place and route tools.
Knowledge of FPGA architectures.
Experience with FPGA design tools.
Understanding of timing analysis and optimization.
Knowledge of verification methodologies (., UVM).
Experience with simulation tools.
Ability to write test benches and develop test plans
Tools:
Synthesis Tools:
Synopsys Design Compiler: A widely used synthesis tool.
Cadence Genus Synthesis Solution: Another industry-standard tool.
Xilinx Vivado: Includes synthesis tools for Xilinx FPGAs.
Intel Quartus Prime: Includes synthesis tools for Intel FPGAs.
Simulators:
Verilator:
Icarus Verilog: A free and open-source Verilog simulation and synthesis tool.
For any further query kindly contact: Hemath Kumar :-.
Job Types: Full-time, Internship
Contract length: 21 months
Pay: ₹160, - ₹430, per year
Benefits:
Health insurance
Provident Fund
Schedule:
Day shift
Supplemental Pay:
Performance bonus
Work Location: In person
Application Deadline: 15/03/2025