Role Description:
A DFT architect role. The incumbent will be responsible for leading the execution and sign-off of DFT/DFD/DFM (design for test/debug/manufacturability) activities for developing innovative products for automotive. The candidate selected will also be involved in all aspects of DFT including methodology development, design, pattern development, manufacturing tests and debug.
The incumbent should be self-driven, adaptable, flexible, creative and capable of working independently. He/she needs to be a solution orientated individual with a quality driven and customer focused mindset.
Responsibilities include but not limited to:
· Strong DFT Fundamentals, so as to be a Technical Mentor to the youngsters
· SoC DFT leadership for at least one complex SoCs, including silicon bring-up and debug
· DFT architecture specification
· DFT planning, tracking and reporting
· DFT RTL coding and integration
· Scan, memory and Logic-BIST architecture specification and implementation
· High Speed interface DFT management
· Interaction with Front End, Back End &Test Engineers located at various sites
Technical background/Key Skills:
· Qualification: Bachelors/Masters in Electronics
· Good RTL (VHDL or Verilog) writing skills
· SOC integration and RTL modification as per DFT requirement
· Experience on analog testing and low-pin-count testing
· Hands on experience with JTAG protocols, Scan and MBIST architectures and tools
· Working Knowledge in scripting language and latest technology, eg, advance fault models, low power ATPG, analog Bist, Logic Bist will be preferred
· Expertise to use industry standard tools like Tetramax, Design Compiler, etc.
· Expert leader in ATPG coverage analysis to achieve high test coverage at SoC level.
· Experience in follow-up/closure of tool issues with EDA CAD vendors
· Strong teamwork and
4 - 10 Years
5 Openings
0.8-1.3 Lac/Yr
Face-to-Face interview
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