Managers ASIC (Design Verification )

Tessolve Semiconductor

3 - 9 Years
15 Openings
Not Disclosed
Hyderabad
+2 Bangalore, Chennai
Face-to-Face interview

Key Skills

Uvm System Verilog SOC IP PCIE Mipi Zebu Work From Home

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Job Description

• IP verification Using SV/UVM

• SOC Verification using C/SV

• Third Party VIP Integration

• Interconnect Protocols: AHB, AXI, APB

• SOC Interfaces: GPIO, SPI, I2C, UART (3+)

• High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+)

• Memory Interfaces: DDR or HBM I/O (10+)

• Coverage Closure: Code, Functional and Toggle

• Tools: Synopsys VCS or Cadence Incsive

• Technical Documentation: Testbench Specification, Test Plan Specification

• Foundry Porting Experience: Technology Library Conversion Related Changes Verification

Experience
3 - 9 Years
No. of Openings
15
Education
Professional Degree
Role
Design & Verification Engineer
Industry Type
IT-Hardware & Networking / IT-Software / Software Services
Gender
[ Male / Female ]
Job Country
India
Type of Job
Full Time
Work Location Type
Work from Home

About Tessolve Semiconductor

Having started our journey in 2004, we are into the 18th year of Tessolves semiconductor engineering. Its an important milestone that reflects our capability as a partner for semiconductor OEMs and associated technology and electronics manufacturers. The company is on track to be the worlds No. 1 semiconductor solutions company in the next five years. With 2600+ employees worldwide, Tessolve provides a one-stop-shop solution with complete hardware and software capabilities and advanced silicon and system testing labs. As the top semiconductor solutions company, we plan for tomorrows customers with specific initiatives in 5G, mmWave, Silicon Photonics, High-Performance Compute, System-level Test, Automotive Products, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Automotive, Industrial, Avionics, IoT, and Medical segments.