As a Senior Datapath Design Engineer for Non-Volatile Memory Datapath Functional Group , you will support design and validation activities of datapath and high-speed I/O interfaces of Flash Memory (non-volatile memory) products. In this highly challenging role you will be engaged in high speed circuits block level and sub-system level design and timing optimization and supervising their layout. You will be working with project teams to understand fullchip floorplan and how to fit and place your circuits in fullchip level. You will be also working with Application Engineering team to understand the new specs and translate them into circuit requirements. You will also work with CMOS/modeling team to define CMOS characteristics to realize and enable high-speed circuits. In addition to design activities you will be heavily engaged in high speed circuits functional and timing validation from base cells all the way to full-chip level using wide variety of simulation tools such as HSPICE, Fast SPICE and ncverilog. Last but not least you are responsible for documenting block level and sub-system level Micro-Architecture Spec(MAS) in accordance with variety of industry standards such as ISO26262. A deep understanding and knowledge of high frequency digital, analog and mixes signal circuit design, CMOS device physics, CMOS circuits power consumption concepts and pipeline structures are necessary.